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Essential VHDL is a great follow-on book that deepens your understanding of VHDL and shows how to get the most from your VHDL synthesizer.  It covers the following topics:
  • Demonstrates practical synthesis techniques
  • Contains several real-world design examples
  • Illustrates synthesis results using gate-level circuits
  • Focuses on the std_logic type and its related functions
  • Discusses, in detail, state machines, partitioning and hardware creation
  • Includes the recently approved 1076.3 standard (numeric_std)

Essential VHDL Table of Contents

  1. VHDL Basics
  2. Design Topics
  3. Advanced Issues
1. VHDL Basics
  1. What is VHDL?
  2. Black Boxes
  3. Connecting Black Boxes
  4. Naming and Labeling
  5. Implementing Basic Logic
  6. Ordering of Statements
  7. Design for RTL Synthesis
  8. Different Styles of Design Description
2. Getting Your First Design Done
  1. Defining the Black Box
  2. The Entity
  3. The Architecture
    1. Dataflow Design
    2. Structural Design
    3. Behavioral Design
3. Gates, Decoders and Encoders
  1. Gates
    1. Gates Using Structural Instantiation
    2. Gates Using Concurrent Assignments
  2. Decoders
    1. Decoders Using Concurrent Assignments
    2. Decoders Within a Process Using the case Statement
    3. Decoders Using
    4. Decoders Using if...then
    5. The Difference Between if...then and case Statements
    6. Factorization: Where the Tool Meets the Road
  3. Encoders
4. Registers and Latches
  1. Registers
    1. Structural Instantiation of Flip-flops
    2. Behavioral Inference of Flip-flops
    3. Using the wait Statement
    4. Flip-flops with Enable
    5. Flip-flops with if...then and a Sensitivity List
    6. Key Differences Between if...then and wait-Generated Flip-flops
    7. Flip-flop Reset and Preset
    8. Asynchronous Resets and Presets
    9. Synchronous Resets and Presets
    10. Notable Issues with Sets and Resets
  2. Latches
    1. Structural Instantiation of Latches
    2. Latches Using Concurrent Assignments
    3. Latches Using Processes
    4. Key Differences Between Processes and Dataflow Inferred Latches
5. Counters and Simple Arithmetic Functions
  1. Arithmetic Functions in Predefined Packages
  2. Load-able and Enable-able Counters
  3. Operator Overloading
  4. Vector Direction
  5. Functions Available in the Standard Packages
  6. Adders and Subtractors
  7. Multiplication, Division and Exponentiation
  8. Design Example
6. Finite State Machines
  1. Typical State Machine Blocks
  2. State Machine Inputs and Outputs
  3. Developing the State Diagram
  4. Creating a Type for Your States
  5. Coding the Next State Conditioning Logic
  6. Registering the Current State Vector
  7. Coding the Output Conditioning Logic
  8. The Complete PCI Target State Machine Design
  9. State Machines as Part of Your System Design
    1. Determine the Datapath
    2. Determine the Control Algorithm
    3. Defining the Black Box
    4. Describe the States Using the Enumerated Types
    5. Code the Next State Conditioning Logic
    6. Code the Current State Register
    7. Code the Output Conditioning Logic
    8. Integrate with the Datapath
  10. Issues Related to State Machine Design Technique
7. Resets, Presets, Tri-state and Bi-directional Signals
  1. Asynchronous Presets and Resets
    1. Structural Instantiation of a Flip-flop with Preset and Reset
    2. Behavioral Coding of a Flip-flop with Preset and Reset
    3. Using Asynchronous Presets/Resets to Load a Flip-flop
  2. Tri-states
    1. Tri-state Buffer Using Structural Instantiation
    2. Tri-state Buffer Using Concurrent Assignment
    3. Tri-state Buffer Using if...then Statements
    4. Enabling or Disabling a Bus Using Aggregates
  3. Bi-directional Buffers
    1. Bi-directional Buffer Using Structural Instantiation
    2. Bi-directional Buffer Using Concurrent Assignment
    3. Design Example
8. Understanding Hardware Creation
  1. Signals Have Implicit Memory
  2. The Last Signal Assignment is the One that Takes Effect
  3. Implicit Latch Inference
    1. Unwanted Implicit Latches
    2. Completely Specifying if...then Statements to Avoid Implicit Latches
    3. Completely Specifying All Outputs of a case Statement to Avoid Implicit Latches
    4. Implicit Memory from Lack of a Reset or Preset to a Flip-flop
  4. Don't Care Comparisons and Assignments
    1. Don't Cares in Wildcard Comparisons
    2. Don't Care Output Assignment
  5. Resolution Functions, Tri-states and Muxes
  6. Resource Sharing
9. Design Partitioning
  1. Design Hierarchy
  2. Hierarchy in VHDL
    1. Positional Versus Named Association for Component Instances
    2. Leaving an Output Port Unconnected
  3. Libraries
    1. Adding Components to Libraries
  4. Packages
  5. Component Configuration
  6. Partitioning Techniques that Influence Implementation


10. Getting the Most from Your State Machines
  1. State Encoding
    1. Sequential State Encoding
    2. Equation 1: Equation for the Number of Encoded States
    3. Explicitly Encoding States Sequentially
    4. Analyzing the Next State Logic
    5. Number and Complexity of Branch Conditions
    6. Number of State Bits
    7. Reducing the Number of State Bit Transitions When Going From State to State
    8. One-hot Coded State Machines
    9. Explicit Method for One-hot Coded State Machines
    10. Step 1: Creating the Type for the State Machine
    11. Step 2: Set the Default State for the State Vector
    12. Step 3: Replace case with if...then for the nextState Assignment
    13. Step 4: Change the Code for the Idle State Condition in the Current State Process
    14. Step 5: Replace case with if...then for the Output Conditioning Logic
    15. State Encoding Guidelines for Performance
    16. Design Implications of State Encoding
    17. Other Issues When Explicitly Assigning State Bits
  2. Output Decoding
    1. Default Output Assignment
    2. Registered Outputs
    3. Don't Cares
    4. Directly Encoding Outputs
    5. Design Considerations for Outputs
11. Scalable and Parameterizable Design
  1. VHDL Facilitates Scalable and Parameterizable Design
  2. Unconstrained Arrays
  3. Generics
  4. Variables
  5. Loops
  6. Attributes
  7. The Generate Statement
    1. Similarity Between for...loop and for...generate
    2. Conditional Generate Statements
12. Enhancing Design Readability and Reuse
  1. Functions
  2. Standard Functions
    1. User-defined Functions
  3. Procedures
    1. Disadvantages of Using Subprograms
  4. Aliases
13. Creative Potpourri
  1. Aggregates
  2. Concatenation
  3. Records
  4. Multidimensional Arrays
  5. Array Indexing Using Enumerated Types
  6. While Loops
  7. Signal Mode Buffer
14. Simulation and Design Verification
  1. Simulation Modeling
  2. Modeling a Simple Gate
  3. Enhancing the Basic Model
  4. Adding Debug Messages to the Model
  5. Hierarchy and Wire Delays
  6. Design Verification
  7. Basic Anatomy of a VHDL Testbench
  8. Reading and Writing Text
  9. Testbench Incorporating Vectors as an Array
  10. Testbench with Vectors in a Separate Text File
Appendix A: Measuring Performance and Utilization
References and Sources