Josh Blum, Robert E. Jenkins - Johns Hopkins Univ. ECE Department
This package and components provide generic LFSR Maximal-Length operation for any length from 3 to 168. Except 37! If you need a register width of 37 you are on your own, since we were too lazy to add a special case for 6 taps. The package contains all the constants and functions needed to use the two components included in the file:
The lfsr entity that decodes the LFSR state to pulse the output clock like a modulo N clock divider. From the generic division parameter N, the LFSR width and the decode value are automatically computed as compile time constants. The LFSR operates on the clock rising edge for any generically supplied shift register WIDTH. It ports out the register state and the PRN output bit. These can be externally latched if desired on the falling edge of the LFSR clock, since the shifts occur on the rising edge.
The lfsr_div entity will select the minimum sized LFSR to divide the input clock with a decoded, modulo-N LFSR operation restricted to N less than 10,000. The reason for the restriction is to avoid the notorious ISE exception error occuring with large for-loops, that arises while computing a decode state. We know ISE 9.2 works up to N=10_000 for our environment, but may trigger the exception for yours. If so, you can just instantiate two cascaded lfsr_div components to complete the division. If the DIVISOR is exactly 2**N-1, then this problem never arises, since the decode state is just the final rollover state, which is easy to find for any length.
XILINX Application Note XAPP 052, Peter Alfke, July 7, 1996.
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