This little audio application tries to imitate the chimes of Big Ben, London.
The chime synthesizer consists of the following modules:
This module instantiates the other modules in the usual way. It has a single input (12 MHz FPGA clock) and a single output (a pulse-density modulated signal) which is fed into an RC low-pass filter. This in turn is connected to an audio amplifier.
I use one of the DCMs to generate the 100 Mhz system clock from the 12 MHz clock input. System reset is also generated here.
A prescaler divides the clock frequency. Its output drives an FSM, which sequences through the notes. A first map translates the state of the FSM to a note number, a second one maps that to the sound parameters for the synthesizer.
I built a sloppy imitation of a 2-operator FM (frequency modulation) synthesizer, because such a device can produce bell sounds easily. I started from a CSOUND description which I found here ( http://www.adp-gmbh.ch/csound/fm/bell.html ), translated that to a C program that computes the sound with floating point operations, and finally simulated real hardware (only integer operations, lookup tables with interpolation for sine and exp tables, etc). You can find all the intermediate representations of the synthesizer in the subdirectory tools.
The XuLA board does not have a DA-converter. But it is very well capable of producing a pulse-density modulated signal, computed by a delta-sigma modulator with minimal effort. Due to the high pulse rate of 100 MHz, a very simple first-order low-pass filter can do the necessary integration of the pulses (see below).
In principle, a simple RC combination is sufficient. In my case, however, I had to attenuate the signal somewhat, because my audio amplifier was too sensitive. So I added another resistor parallel to the capacitor. The attenuation is of course R2/(R1+R2), but note that the time constant changes from RC to C*R1*R2/(R1+R2). I used R1 = 12k, R2 = 3.3k, C = 4.7nF, where R1 is connecting the FPGA pin to the audio output, and from that, R2 is mounted parallel to C, both connected to GND.
You can download the source files for this example design from the XESS website at http://www.xess.com/projects/BigBen.tar.gz .
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Hellwig Geisse - Hellwig.Geisse@mni.fh-giessen.de
Copyright (c) 2011 Hellwig Geisse All rights reserved.
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02/12/2011 - Initial release.