Essential VHDL - RTL Synthesis Done Right

Essential VHDL is a great follow-on book that deepens your understanding of VHDL and shows how to get the most from your VHDL synthesizer.  It covers the following topics:

• Demonstrates practical synthesis techniques
• Contains several real-world design examples
• Illustrates synthesis results using gate-level circuits
• Focuses on the std_logic type and its related functions
• Discusses, in detail, state machines, partitioning and hardware creation
• Includes the recently approved 1076.3 standard (numeric_std)

Essential VHDL Table of Contents
Preface
VHDL Basics Design Topics Advanced Issues
1. VHDL Basics
What is VHDL? Black Boxes Connecting Black Boxes Naming and Labeling Implementing Basic Logic Ordering of Statements Design for RTL Synthesis Different Styles of Design Description
2. Getting Your First Design Done
Defining the Black Box The Entity The Architecture Dataflow Design Structural Design Behavioral Design
3. Gates, Decoders and Encoders
Gates Gates Using Structural Instantiation Gates Using Concurrent Assignments Decoders Decoders Using Concurrent Assignments Decoders Within a Process Using the case Statement Decoders Using with...select Decoders Using if...then The Difference Between if...then and case Statements Factorization: Where the Tool Meets the Road Encoders
4. Registers and Latches
Registers Structural Instantiation of Flip-flops Behavioral Inference of Flip-flops Using the wait Statement Flip-flops with Enable Flip-flops with if...then and a Sensitivity List Key Differences Between if...then and wait-Generated Flip-flops Flip-flop Reset and Preset Asynchronous Resets and Presets Synchronous Resets and Presets Notable Issues with Sets and Resets Latches Structural Instantiation of Latches Latches Using Concurrent Assignments Latches Using Processes Key Differences Between Processes and Dataflow Inferred Latches
5. Counters and Simple Arithmetic Functions
Arithmetic Functions in Predefined Packages Load-able and Enable-able Counters Operator Overloading Vector Direction Functions Available in the Standard Packages Adders and Subtractors Multiplication, Division and Exponentiation Design Example
6. Finite State Machines
Typical State Machine Blocks State Machine Inputs and Outputs Developing the State Diagram Creating a Type for Your States Coding the Next State Conditioning Logic Registering the Current State Vector Coding the Output Conditioning Logic The Complete PCI Target State Machine Design State Machines as Part of Your System Design Determine the Datapath Determine the Control Algorithm Defining the Black Box Describe the States Using the Enumerated Types Code the Next State Conditioning Logic Code the Current State Register Code the Output Conditioning Logic Integrate with the Datapath Issues Related to State Machine Design Technique
7. Resets, Presets, Tri-state and Bi-directional Signals
Asynchronous Presets and Resets Structural Instantiation of a Flip-flop with Preset and Reset Behavioral Coding of a Flip-flop with Preset and Reset Using Asynchronous Presets/Resets to Load a Flip-flop Tri-states Tri-state Buffer Using Structural Instantiation Tri-state Buffer Using Concurrent Assignment Tri-state Buffer Using if...then Statements Enabling or Disabling a Bus Using Aggregates Bi-directional Buffers Bi-directional Buffer Using Structural Instantiation Bi-directional Buffer Using Concurrent Assignment Design Example
8. Understanding Hardware Creation
Signals Have Implicit Memory The Last Signal Assignment is the One that Takes Effect Implicit Latch Inference Unwanted Implicit Latches Completely Specifying if...then Statements to Avoid Implicit Latches Completely Specifying All Outputs of a case Statement to Avoid Implicit Latches Implicit Memory from Lack of a Reset or Preset to a Flip-flop Don't Care Comparisons and Assignments Don't Cares in Wildcard Comparisons Don't Care Output Assignment Resolution Functions, Tri-states and Muxes Resource Sharing
9. Design Partitioning
Design Hierarchy Hierarchy in VHDL Positional Versus Named Association for Component Instances Leaving an Output Port Unconnected Libraries Adding Components to Libraries Packages Component Configuration Partitioning Techniques that Influence Implementation
10. Getting the Most from Your State Machines
State Encoding Sequential State Encoding Equation 1: Equation for the Number of Encoded States Explicitly Encoding States Sequentially Analyzing the Next State Logic Number and Complexity of Branch Conditions Number of State Bits Reducing the Number of State Bit Transitions When Going From State to State One-hot Coded State Machines Explicit Method for One-hot Coded State Machines Step 1: Creating the Type for the State Machine Step 2: Set the Default State for the State Vector Step 3: Replace case with if...then for the nextState Assignment Step 4: Change the Code for the Idle State Condition in the Current State Process Step 5: Replace case with if...then for the Output Conditioning Logic State Encoding Guidelines for Performance Design Implications of State Encoding Other Issues When Explicitly Assigning State Bits Output Decoding Default Output Assignment Registered Outputs Don't Cares Directly Encoding Outputs Design Considerations for Outputs
11. Scalable and Parameterizable Design
VHDL Facilitates Scalable and Parameterizable Design Unconstrained Arrays Generics Variables Loops Attributes The Generate Statement Similarity Between for...loop and for...generate Conditional Generate Statements
12. Enhancing Design Readability and Reuse
Functions Standard Functions User-defined Functions Procedures Disadvantages of Using Subprograms Aliases
13. Creative Potpourri
Aggregates Concatenation Records Multidimensional Arrays Array Indexing Using Enumerated Types While Loops Signal Mode Buffer
14. Simulation and Design Verification
Simulation Modeling Modeling a Simple Gate Enhancing the Basic Model Adding Debug Messages to the Model Hierarchy and Wire Delays Design Verification Basic Anatomy of a VHDL Testbench Reading and Writing Text Testbench Incorporating Vectors as an Array Testbench with Vectors in a Separate Text File
Appendix A: Measuring Performance and Utilization
Index
References and Sources