Several people mentioned problems getting the JTAG port to work through the Xchecker port of the XSV Board. I have placed two new designs onto the Design Examples page on the XESS website (/design_examples.php):

1. Design files and documentation for the XSV CPLD that enables the Xchecker interface. My suspicion is the problems were caused when the outputs of the Flash RAM on the XSV Board got enabled and interfered with the JTAG signals. This design takes care of that problem.
2. Design files and documentation for the XSV CPLD that makes it emulate a Xilinx Parallel Cable III interface. This lets you use the Hardware Debugger and JTAG Programmer tools in Xilinx Foundation to program/debug the XSV Board through the simple XESS downloading cable. So you don't have to use GXSLOAD to download bitstreams to the XSV Board and you should be able to use tools like Chipscope with the XSV Board.