Date: Feb 18, 2000
I have been having problems with my XS40 design not functioning at all for the past few weeks. I finally tracked down the problem, I had an I/O signal to p16. I moved it to p50 and now everything works great. Any suggestions why p16 would not work? The xc4010xl data sheet says that it is an I/O pin, and the XS40 does not use this pin at all as far as I can tell.
I have the uC and SRAM disabled in my design. When I said that the design did not function at all, I litteraly mean that internal circuits which had no dependence on the bad pin were acting as if the clock was not running.
Do you have a V1.3 XS40 Board? If so, then P16 (TCK) is attached to pin P73 (CCLK). If some external circuit was holding P16 at logic 1 or logic 0, then CCLK would not toggle and the FPGA could never be loaded with a bitstream.
In V1.4 and later versions, P16 and P73 are no longer connected. I'm not sure why you would have experienced the problem you describe if you are using a V1.4 board.