I have appended some pin assignments and code from one of our customers who made the modifications for accessing the RS232 driver through the CPLD. This code should be compiled and loaded into the CPLD, not the FPGA.

  net V_tck loc=p4;
  net V_initb loc=p9;
  net V_done loc=p10;
  net V_progb loc=p11;
  net V_cclk loc=p12;
  net V_m(0) loc=p13;
  net V_m(1) loc=p14;
  net V_m(2) loc=p15;
  net V_d(0) loc=p32;
  net V_d(1) loc=p33;
  net V_d(2) loc=p34;
  net V_d(3) loc=p35;
  net V_d(4) loc=p36;
  net V_d(5) loc=p37;
  net V_d(6) loc=p39;
  net V_d(7) loc=p40;
  net V_a(0) loc=p16;
  net V_a(1) loc=p17;
  net V_a(2) loc=p18;
  net V_a(3) loc=p19;
  
  net TXD1 loc=p24;
  net RTS1 loc=p25;
  
  
  net RXD1 loc=p28;
  net CTS1 loc=p29;
  
  
  net ceb loc=P46;
  
  
  
  
  net resetb loc=p3;
  
  
  
  net ppd(0) loc=p77;
  net ppd(1) loc=p74;
  net ppd(2) loc=p72;
  net ppd(3) loc=p70;
  net ppd(4) loc=p68;
  net ppd(5) loc=p67;
  net ppd(6) loc=p66;
  net ppd(7) loc=p65;
  net ppc(0) loc=p79;
  net ppc(1) loc=p78;
  net ppc(3) loc=p71;
  net pps(3) loc=p76;
  net pps(4) loc=p60;
  net pps(5) loc=p61;
  net pps(6) loc=p64;
  
  net rxd loc=p80;
  net txd loc=p81;
  net rts loc=p82;
  net cts loc=p85;
  
  -- VHDL code for the XSV CPLD
  library ieee;
  use ieee.std_logic_1164.all;
  
  entity dwnldpar is
   port(
  -- parallel port data, control, and status pins
          ppd: in std_logic_vector(7 downto 0);
          ppc: in std_logic_vector(3 downto 0);
          pps: out std_logic_vector(6 downto 3);
          
          -- Virtex FPGA pins
          V_a: in std_logic_vector(3 downto 0); -- inputs from Virtex
          V_tck: out std_logic; -- driver to Virtex JTAG clock
          V_cclk: out std_logic; -- driver to Virtex config clock
          V_progb: out std_logic; -- driver to Virtex program pin
          V_initb: in std_logic; -- input from Virtex init pin
          V_done: in std_logic; -- input from Virtex done pin
          V_d: out std_logic_vector(7 downto 0); -- drivers to Virtex data pins
          V_m: out std_logic_vector(2 downto 0); -- Virtex config mode pins
          
          ceb: out std_logic; -- Flash chip-enable
          resetb: out std_logic; -- reset for video input and Ethernet chips
          bar: out std_logic_vector(9 downto 0); -- LED bargraph
          
          -- serial port connections
          rxd: in std_logic;
          txd: out std_logic;
          rts: out std_logic;
          cts: in std_logic;
          
          --Virtex FPGA pins
          RXD1: out std_logic;
          TXD1: in std_logic;
          RTS1: in std_logic;
          CTS1: out std_logic
      );
  end dwnldpar;
  
  architecture dwnldpar_arch of dwnldpar is
          constant LO: std_logic := '0';
          constant HI: std_logic := '1';
          constant SLAVE_SERIAL_MODE: std_logic_vector(2 downto 0) := "111";
          
          begin
          -- disable other chips on the XSV Board so they don't interfere
          -- during the configuration of the Virtex FPGA
          ceb <= HI; -- disable Flash
          V_tck <= LO; -- deactivate Virtex JTAG circuit
          
          -- disable the video input and Ethernet chips until config is done
          resetb <= LO when V_done=LO else HI;
          
          -- connect Virtex configuration pins
          V_m <= SLAVE_SERIAL_MODE; -- set Virtex config mode pins
          V_progb<= ppc(0); -- Virtex programming pulse comes from parallel port
          V_cclk <= ppc(1); -- Virtex config clock comes from parallel port
          -- config bitstream comes from parallel port control pin until
          -- config is done and then gets driven by parallel port data pin
          V_d(0) <= ppc(3) when V_done=LO else ppd(0);
          
          -- connect the rest of the parallel port to the Virtex FPGA
          V_d(7 downto 1) <= ppd(7 downto 1); -- data from PC
          pps(6 downto 3) <= V_a(3 downto 0); -- status back to PC
          -- display status of Virtex done and init pins on the bargraph LED
          bar(0) <= V_done;
          bar(1) <= V_initb;
          
          --connect serial port to virtex FPGA
          RXD1 <= rxd;
          txd <= TXD1;
          rts <= RTS1;
          CTS1 <= cts;
  end dwnldpar_arch;