The XS40 schematic shows the RST/OE pin (with OE active low) of the AT17C256 connected to pin 41 of the XC4005. This is the INIT pin (active low) which, according to my potentially flawed reading of the Xilinx datasheet, is normally high during configuration in Master Serial mode (as the 4005 is configured on the XS40 board), and only goes low to indicate an error during configuration. If this is true, then it would not correctly drive the RST/OE pin, unless the polarity of the RST/OE pin is reversed (OE active high). This is an option according to the Atmel datasheet for the AT17C256, but they say it's determined by the device programmer. Does Xess reverse this polarity during programming, or is there something else going on?