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Question & Answer
Classification:
Date: Mar 12, 2001
How do we use P0 and P2 of the 8031 on the XS Board?
Q:
We are working with the xs40010xl+, 80C32 processor. We are programing in a C-compiler and we wonder how we use P0,P2 (port 0 & 2) as an inport (and outport) from the FPGA. We can use port no. 1, P1, but P0 and P2 are connected to the SRAM.
A:
P0 and P2 are needed to send address and data to the RAM. The 8032 uC is ROMless, so the RAM is the only place for it to get instructions. So the P0 and P2 ports cannot be made available for use as general-purpose I/O.
You could replace the 8032 with an 8052 which has a program stored in internal ROM or Flash. Then the uC could fetch instructions from its internal store and use the P0 and P2 ports as general-purpose I/O. Of course, you need some equipment to program the 8052 and you need to insert and remove the uC chip each time you want to change the program.
Q:
Another question: after configuration is completed, the processor's program is immediately restarted. Is it supposed to be that way?
A:
With the exisiting FPGA+uC interface circuit loaded into the FPGA, the uC starts running as soon as the FPGA gets configured. You could reprogram the FPGA+uC interface so that the FPGA holds the uC in the reset state until you want it released.
You should also make sure your program stops executing when it completes (e.g., sits in an infinite loop), or else it will just keep incrementing the program counter (executing whatever garbage is in RAM beyond your program on power-up) until it loops over ... and starts executing your program again.