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Question & Answer
Classification:
Date: Mar 12, 2001
Contention between the CPLD and Virtex FPGA on the XSV Board
Q:
I have a questions concerning Virtex (e.g. pin 157) and CPLD (pin 27) driving the same LED on the board.
If both are configured as outputs and have different signals high and low, will this destroy the IC's ?
A:
Yes, it definitely could do that. By default, the CPLD is programmed with the dwnldpar.svf file which makes the CPLD drive the left-most LED digit on the XSV Board with the value on the parallel port data pins. The Virtex FPGA and Flash RAM also share these pins, so only one of these devices should be enabled at a time. If you want to use the left-most LED digit, you have to edit the dwnldpar.vhd file to disable the outputs and compile/load the new SVF into the CPLD.
Q:
Do I have to care about unused pins of the CPLD and the Virtex? (Pins not mentioned in the ucf-file and vhdl-file) Can undefined I/O's destroy the board?
A:
Unused FPGA and CPLD pins will be placed in a high-impedance state so they should not cause damage to other components.