|
Question & Answer
Classification:
Date: Feb 22, 2001
Explanation of serial EEPROM/FPGA connections on the XS40 Board
Q:
We tried to use the serial EEPROM AT17C256 for programming a XC4010E on the XS40V1.2 Board. But there was no data stream from EEPROM to the FPGA, no functionality.
During a closer look at the V1.2 Schematic, we found that Pin 4 (CE\) of U7 is connected to XCBUS30 and PIN30 (M1) of the FPGA, U1. Is this correct?
According to the Xilinx databook, Pin 4 of U7 should be connected to the
- DONE Signal of the FPGA, that means PIN53 of a XC4010E-PC84 or
- LDC\ Signal of the FPGA, that means PIN37 of a XC4010E-PC84.
Please check the circuitry and give us your idea.
A:
We could not use the standard connections for the serial eeprom due to constraints caused by other circuitry on the XS40 Board. We connected /CE to the M1 pin of the FPGA because M0=M1=M2=0 when the FPGA is in master-serial mode and the low logic level on M1 also enables the serial eeprom. The eeprom stays selected after configuration is complete, but this doesn't really matter unless you want to use the DIN pin of the FPGA. And we connected the RST/OE pin to the FPGA's INIT pin since the INIT pulses low at the start of configuration. The low pulse resets the serial eeprom address counter and then the high level on INIT keeps the eeprom output enabled during configuration.
I'm not sure which version of the XSTOOLs software you are using. Early versions failed to program the proper polarity for the eeprom RST/OE pin. This would prevent the eeprom from outputing data during configuration. You might try the latest version of GXSLOAD and see if that programs your serial eeprom correctly.