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Question & Answer
Classification:
Date: Jan 11, 2001
Contention between the CPLD and Virtex FPGA on the XSV Board
Q:
On an XSV300 board, there are lines that are shared by the CPLD and the Virtex FPGA that are used to drive the two 7-segment displays (and also the Flash RAM, if it is enabled). When the CPLD is configured with the usual parallel port interface, using the file "dwnldpar.svf", it seems that the CPLD drives the left-side 7-segment display with the logic values that are on bits D0 to D7 of the parallel port. (I'm basing this assumption on my reading of the "XSV Parallel Port Interface" application note from XESS). If the Virtex also tried to drive the left-side 7-seg display then it would seem to me that either the CPLD or the Virtex would be at risk of damage from the other.
My question is therefore: Should the Virtex not drive the 7-segment displays (esp the left-side display) unless the CPLD is congifured differently to its "default" configuration as contained in "dwnldpar.svf"?
A:
The dwnldpar.svf file provides an interface between the parallel port and the FPGA through the CPLD. The parallel port data lines are passed through the CPLD to the FPGA on the wires that interconnect the Flash data pins and the left 7-segment LED with the CPLD and FPGA. So there is going to be a contention if the FPGA tries to drive these lines for any reason.
You can program the CPLD with the dwnldtst.svf file to eliminate the contention. This CPLD design tristates the pins which drive the LED, Flash, and FPGA pins after the FPGA configuration is completed. You no longer have access to the parallel port from the FPGA, but the FPGA has contention-free access to the LED now.