You can download the XSV V1.0 Manual and look on page 32 to read about this. Here is a summary:

Header J21 provides an interface between the FPGA and an Xchecker cable. The Xchecker cable can be used to perform configuration and readback operations on the FPGA. To prevent interference with the Xchecker cable, the CPLD should be erased or the pins in the table below should be tristated when the CPLD is active. To prevent interference, the shunt should be removed from jumper J36 to disconnect the DS1075 and any external clocks from the clock input by the Xchecker cable (CLKI). You should also erase the CPLD or make sure the CPLD pins in the table below are tristated.

Xchecker Pin   Virtex FPGA Pin   CPLD Pin
1 – VCC (+5V)    N/A               N/A
2 – RT           132               16
3 – GND          N/A               N/A
4 – RD           133               17
6 – TRIG         139               18
7 – CCLK         179               12
9 – DONE         120               10
10 – TDI         167               33
11 – DIN         177               32
12 – TCK         239               4
13 – PROGRAM     122               11
14 – TMS         156               35
15 – INIT        123               9
16 – CLKI        89                22
17 – RST         144               20
18 – CLKO        141               19

If you want to access the JTAG port of the FPGA, all the requisite pins are already connected to the Xchecker interface except for TDO. The TDO pin of the FPGA connects to pin 34 of the CPLD, so you must route the signal through the CPLD and onto the RD pin of the Xchecker interface (which the Xchecker uses for TDO). You must also make sure that pins 133 and 163 on the FPGA are tristated in your design or else they will override TDO.

There are additional documents and design files for using the Xchecker interface on the XSV Board.