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Question & Answer
Classification:
Date: Mar 14, 2000
Using the Spartan FPGA Mode pin as an input
Q:
I have targeted some examples from the Practical Xilinx Designer Lab Book to the Spartan family. In the 8-bit parity generator example, I edited the user-constraint file where I intentionally assigned a net to pin 60
NET B<1> LOC=P60;
This pin is the MODE pin of the Spartan device. Obviously, when I tried to compile the design, the compiler shows an error telling me that a non-constrainable site has been used. The book shows that the solution is to create a macro, open an schematic in order to use the macro and connect special symbols (like MD0, MD1) to the macro input pins.
This solution works well when I target the design to the XC4000 family because the XC4000 library contains the special symbols. However, when I target the design to the Spartan family, the Spartan Library does not contain a special symbol (MODE) to connect it to the macro.
What symbol should I use to connect the MODE pin to the NET B<1>? May I include the XC4000 Library in my project and use the MD0 simbol?
A:
The XC4000 series has three mode pins which are also useable as two inputs and an output after the device is configured. The Spartan has one mode pin and it cannot be used as an input or an output after configuration. So you cannot access all 8 data pins of the parallel port when using a Spartan device in an XS Board. That's just the way it is...