Address bit order for the XS40 Board RAM

Q:

I've significant trouble reading the content of the XS40-board RAM. Loading the attached hex_code.hex file the RAM content is only rubbish. A small VHDL-program which is loaded in to the FPGA contains an address counter and the control of the RAM-control signals. Here are the pin assignments I am using:

NET D0 LOC=P41;
NET D1 LOC=P40;
NET D2 LOC=P39;
NET D3 LOC=P38;
NET D4 LOC=P35;
NET D5 LOC=P81;
NET D6 LOC=P80;
NET D7 LOC=P10;
NET A0 LOC=P78;
NET A1 LOC=P79;
NET A2 LOC=P82;
NET A3 LOC=P84;
NET A4 LOC=P3;
NET A5 LOC=P5;
NET A6 LOC=P60;
NET A7 LOC=P56;
NET A8 LOC=P58;
NET A9 LOC=P59;
NET A10 LOC=P83;
NET A11 LOC=P4;
NET A12 LOC=P50;
NET A13 LOC=P57;
NET A14 LOC=P51;
NET CLK LOC=P29;
NET RESET LOC=P36;
NET NCS LOC=P65;
NET NWE LOC=P62;
NET NOE LOC=P61;

A:

All your problems probably come from the address bit ordering you are using. XSLOAD loads hex values into the RAM using the address and data bit ordering dicated by the 8051. This insures that the 8051 will fetch valid opcodes from sequential addresses even though the opcodes and their locations may look scrambled from the point-of-view of the RAM. The RAM address and data bits are reordered from their listed locations in order to facilitate layout of the XS40 PWB.

Here are the data and address pin assignments you should use:

NET wr_  LOC=P62;
NET oe_  LOC=P61;
NET ce_  LOC=P65;
NET a0  LOC=P3;
NET a1  LOC=P4;
NET a2  LOC=P5;
NET a3  LOC=P78;
NET a4  LOC=P79;
NET a5  LOC=P82;
NET a6  LOC=P83;
NET a7  LOC=P84;
NET a8  LOC=P59;
NET a9  LOC=P57;
NET a10  LOC=P51;
NET a11  LOC=P56;
NET a12  LOC=P50;
NET a13  LOC=P58;
NET a14  LOC=P60;
NET a15  LOC=P28;
NET ad0  LOC=P41;
NET ad1  LOC=P40;
NET ad2  LOC=P39;
NET ad3  LOC=P38;
NET ad4  LOC=P35;
NET ad5  LOC=P81;
NET ad6  LOC=P80;
NET ad7  LOC=P10;

Question & Answer

Address bit order for the XS40 Board RAM

Q:

A: