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Question & Answer
Classification: FAQ_CLASSIFICATION
Date: FAQ_DATE
8031 microcontroller reset questions
Q:
It says, in one of the documents available in your site, that 8031 reset can be controlled by the parallel port pin D0. But this is not consistent with the schematics or description in "The Practical Xilinx Designer Lab Book".
A:
You have to program the FPLD to direct the logic level on D0 to the FPLD pin that is connected to the 8031 RST pin. Then the 8031 reset logic will be controlled by the level you place on D0.
Q:
Assuming the RST pin of the 8031 is not controlled via the parallel port pin D0, what is the voltage level of the FPLD pin (pin 45 in the XS95 and pin 36 in XS40) connected to RST of 8031 if the FPLD pin is not explicitly programmed?
A:
If you do not explicitly program pin 45 of the CPLD, there is a pull-up that pulls the RST pin of the 8031 to logic 1. On the XS40 Board, there is no pullup so you should program pin 36 of the FPGA to output a high level.
Q:
If I just want to use FPLD without 8031, can I program the pins connected to 8031 for my use? That is, make the 8031 pins to be in high impedance state.
A:
Yes, just keep the 8031 RST pin at a high level and the other 8031 pins will tristate.