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Question & Answer
Classification: FAQ_CLASSIFICATION
Date: FAQ_DATE
Scrambled address/data pins on the RAM and 8031 of the XS Boards?
Q:
I have received my copy of The Practical Xilinx Designer, as well as the current version of your download and I have 1 question: is the schematic for the XS40-005 board correct regarding the connections to the 8031? According to the OKI data sheets I have found, it looks like the upper address lines may be somewhat scrambled. As an example, the sheet shows port 2.0 (pin 24- PLCC package) to be A8. On your schematic, this is XCBUS59 which is connected to the A9 pin of the 32K x 8 SRAM.
A:
Yes, the address bits to the RAM are scrambled with respect to the pin assignments of the RAM. But it makes no difference to the RAM which pin is used for a particular address bit as long as everybody who accesses the RAM uses the same ordering. I mentioned this on page 333 of the book as well.
You can check the address and data line ordering on the schematics.