The upper half of the RAM address connects to both the FPGA and the 8031. When the 8031 is running, the FPGA just tristates its pins so it doesn't interfere.

The data bus of the RAM connects to the FPGA and the muxed lower-address/data bus of the 8031. The FPGA latches the address bits from this bus when ALE is active and then outputs the lower address bits on a separate bus that connects to the lower address pins of the RAM. During the portion of an instruction cycle when the 8031 passes data over the data bus to/from the RAM, the FPGA tristates its drivers so it doesn't interfere. (Of course, it holds the latched address bits stable so the RAM can be reliably accessed.)

The read control line of the 8031 goes into the FPGA and the FPGA develops chip-select and output-enable signals to activate the RAM. (This allows the FPGA to disable the RAM and insert another source of data during read operations.) The 8031 write control line goes directly to the RAM.

You can download a document on interfacing the 8031/FPGA/RAM. There are also a couple of sets of FPGA design files for a simple LED register that the 8031 can write to and a random number generator that the 8031 can seed and read.