Teaching programmers how to use programmable logic like FPGAs: you would think that was easy, right? Chris Felton recently gave a workshop at PyOhio to do just that. The intent was to help programmers learn FPGA programming techniques using the MyHDL Python package. To support his workshop, Chris put together a complete hardware and software setup for the programmers that consisted of:
- A VirtualBox VM with the Xilinx ISE FPGA tools and MyHDL preloaded so it could just be dropped onto the attendees' laptops.
- A set of XESS XuLA-200 FPGA boards plugged into StickIt! boards that could be connected to the laptop USB ports to provide a complete FPGA hardware testbed for each programmer.
- A set of FPGA hardware testbeds made up of XESS XuLA-200 FPGA boards plugged into StickIt! boards that connect to the USB ports of the programmers' laptops.
- Two "Hello, World!" examples written with MyHDL: one for blinking an LED with a pushbutton, and a second variation that registers the LED using a flip-flop.
So how'd it work? Well, unfortunately Chris ran into some unexpected problems:
- The entire workshop was only one hour long.
- The programmers wanted to run all the tools natively on their laptops instead of using the VM, so this ate up some time doing installations.
- Once installed, more time was consumed configuring the licenses required by the Xilinx FPGA tools.
- Finally, although Chris had checked for this problem on multiple OSes beforehand, the programmers' laptop USB ports had "permission denied" issues that blocked their access to the FPGA hardware.
So the programmers didn't get to experience as much fun programming FPGAs as Chris intended, but that doesn't mean you can't! Chris put his PyOhio tutorial for learning about programming FPGAs on bitbucket.org so you can go through it at your own pace. Even if you already have experience with the VHDL/Verilog design flows for FPGAs, you'll appreciate the integration of MyHDL with the rest of the Python ecosystem and the powerful simulation capabilities that makes possible.
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