How to Learn VHDL

Posted by: Dave Vandenbout 6 years ago


As FPGAs work their way into the hobbyist/maker community, I'm guessing a lot of you are trying to learn VHDL and Verilog. (You can try to use schematics, but the Xilinx editor is pretty poor.) Which language you choose is up to you, but I'll only talk about VHDL in this post. There's general agreement that if you know one, it's easy to learn the other.

There's no shortage of VHDL books (around 100 on Amazon) or online tutorials (Google lists 278,000 but I haven't checked them all), so there's no need for me to waste my energy doing another. Instead, what I will do is tell you how to use the existing books & tutorials to learn the use of VHDL in synthesizing logic for FPGAs.

Most online tutorials give you a smattering of VHDL examples that introduce you to about 30% of the language that you need for logic synthesis. (Many of these are written by university instructors trying to get their introductory logic design class up to speed on VHDL.) You can go pretty far with these if you can find examples to use as templates for your own designs. Just google "VHDL tutorial" and you're bound to find something you like in the first few pages of results.

Eventually you're going to need some of the less-obvious features of the language, especially when you want to generalize your designs to make them easier for others to use. For a good, general and (most importantly) concise discussion of VHDL, I like this 54-page appendix from an early edition of Fundamentals of Digital Logic with VHDL Design by Brown & Vranesic (I think). It probably gives you 75% of what you need for doing logic design with VHDL.

Ultimately, though, you'll find your way to Ashenden's The Designer's Guide to VHDL. Aside from reading the actual language specification (please don't do that!), The Designer's Guide is the most complete reference on VHDL. But the current edition weighs in at 3.8 pounds and almost 1,000 pages. That's a lot to go through and it's really not necessary because much of the book discusses language features used for system modeling and simulation, not logic synthesis. (That was the original intent for VHDL; logic synthesis was tacked on later.) So here are my suggestions on what to read in The Designer's Guide if all you want to do is synthesize logic for FPGAs:

  • Chapter 1: Read sections 1.4 & 1.5 to get a general introduction and overview of language elements.
  • Chapter 2: You can use everything here, even the stuff on physical types like time.
  • Chapter 3: Read sections 3.1 through 3.4. If and case statements are the most important things in this chapter. Loops are important, too, but mostly for generating iterative structures.
  • Chapter 4: Like scalars in chapter 2, you should read this entire chapter about arrays and structures.
  • Chapter 5: You can skip the sections 5.2.4, 5.2.5 and 5.2.8 which discuss concepts primarily used for system modeling and simulation. You might also skip section 5.2.7 on concurrent statements because everything you can do with them you can also do with processes. However, you will often see concurrent statements in VHDL so there is a reason to be familiar with them.
  • Chapter 6: Read everything about procedures and functions. These are key features for encapsulating portions of your design to hide details that would obscure the overall function.
  • Chapter 7: Read everything about defining and using packages of modules. These are similar to libraries. Packages will make it easier for others to use your designs.
  • Chapter 8: Skip this chapter. You'll only need to know about resolution functions if you are modeling or simulating the detailed operations of an electronic device.
  • Chapter 9: Read the entire chapter about standard packages like those from IEEE. You'll be spending a lot of time using these in your designs.
  • Chapter 10: You can read this (and other) case studies if you want to see how the VHDL language features are actually used in a more substantial design. Otherwise, skip it.
  • Chapter 11: This is a short chapter, so there's no reason not to read it. I don't use aliases often, but this chapter shows one example where they are really useful. Aliases can also make your design more readable.
  • Chapter 12: Read this entire chapter. Generics let you build general-purpose modules that you can specialize by setting a few parameters when you instantiate them.
  • Chapter 13: Read section 13.1 about defining and instantiating components. This is another concept central to encapsulating and hiding design details and for creating hierarchical systems. You can skip sections 13.2 and 13.3 concerning configurations.
  • Chapter 14: Read this entire chapter to learn how to build circuits using iteration and conditional instantiation.
  • Chapter 15: Skip this chapter. Access types are useful for system modeling and simulation, not synthesis.
  • Chapter 16: You can read this chapter if you want to store/recall data when running a simulation  testbench to exercise your design, but these concepts don't apply to synthesis.
  • Chapter 17: Another case study. Skip it.
  • Chapter 18: You can also skip this chapter; you already have enough of the concepts required to write test benches by now.
  • Chapter 19: Another chapter devoted to concepts applicable to simulation. Skip it.
  • Chapter 20: You should already be familiar with attributes by now, but pay attention to section 20.2 about user-defined attributes because this feature is sometimes used to embed FPGA-specific information into a design.
  • Chapter 21: Well, this is a chapter on design for synthesis, so I guess you should read all of it.
  • Chapter 22: Another case study. Skip it if you want.
  • Chapter 23: You can skip the miscellaneous topics except for section 23.5 which discusses using conversion types in association lists. That's useful for doing inline type conversion when you pass inputs of one type to a module that expects a different type.

Once you're at this point, you know pretty much all you need to describe logic designs for synthesis into FPGAs with VHDL, but not if you want to do it efficiently. For that, you need to read the 176-page Synthesis and Simulation Design Guide written by Xilinx. But don't worry: all you really need to read is chapter 5 about coding VHDL for FPGAs (still, that's about 70 pages). You'll get a whole list of things to avoid that are inefficient or, even worse, not synthesizable at all, as well as tips for how to write things that are efficiently synthesizable into the structures within the FPGA (like block RAMs).

And while you're reading the Synthesis Guide, do the following: build small VHDL projects, synthesize them, and then look at the results using the View RTL Schematic and View Technology Schematic tools available in the Xilinx ISE Project Navigator. Doing this will develop your gut feeling of how your VHDL maps into the FPGA and how small changes to your code can make big changes in how much logic is used. This is the hardware equivalent of looking at the assembly code that's output by a software compiler.

In the end, after going through all this, will you be good at writing synthesizable VHDL? If you already had experience at designing digital logic and had some idea of the internal structure of FPGAs, then I think the answer is yes. If not, then I'm not sure. I know that I continually fall back on my basic knowledge of digital circuits to interpret what the VHDL I'm writing will do. I don't know how you would write VHDL without that mental framework. However, I've heard some say that you can write programs without knowing how a computer works, so maybe there is some hope for doing the same with VHDL. Possibly it will evolve like the programming of embedded microcontrollers: tight, efficient code was of utmost importance when they first appeared with their small RAMs and ROMs, but then less expertise was required when larger memories allowed the use of higher-level languages. It may be that, even today, FPGAs are large enough that you don't have to worry too much about how efficiently you use them. I guess you'll find out.


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