A new VHDL textbook was released a few days ago. *Yawn*, right? There's like a hundred of those on Amazon already.
But the good thing about this one is that it covers the basics of using VHDL in a concise and attractive 129 pages. It goes over the syntax and semantics of the language and illustrates behavioral and structural description styles with an emphasis on synthesis. But you don't have to take my word that this book is good - you can download Free Range VHDL for free!
However, the really exciting thing about Free Range VHDL is not that it's free (although cash-strapped students everywhere might disagree), but that it's offered under a Creative Commons Attribution-ShareAlike license! That means anyone can modify and distribute the text. (Really! You can get the book's LaTeX files and do it right now.)
So what's the big deal about that? Three things:
No more complaining. People love to complain about textbook content: "They didn't cover Mealy FSMs! They short-changed one-hot state encodings!" Well, if you don't like how Free Range VHDL explains something, you can go in there and change it. Then you can redistribute it to your students and others and see if it's really the big improvement you think it is.
No more re-inventing the wheel. Designers often have VHDL techniques that could help others be more productive, but they don't want to go through the effort of writing an entire VHDL textbook just to get to the point where they can describe their technique. But now they can just find the appropriate section of Free Range VHDL and insert their own stuff knowing that all the background scaffolding has already been written.
Good now, better later. As time goes by and contributors make additions and modifications to Free Range VHDL, it will go from being a good VHDL text to a better and better text (provided there is an editor to manage which changes do and don't get into the master branch).
So I'm very encouraged by the introduction of this book. I wonder how long it will be before someone uses it to create Free Range Verilog?