Viewing posts by Dave Vandenbout
Some people have commented that the 12 MHz clock on the XuLA FPGA board is too slow for practical use. What they've missed is the Spartan-3A FPGA has on-chip digital frequency synthesizers (DFS) that can multiply the clock to over 300 Mhz. To show how easy it is to do this, I've added another chapter on using the DFS to my new book about doing FPGA design using Xilinx ISE WebPACK and the XuLA board. It just takes a few lines of VHDL and you can have almost any clock frequency you want between 5 MHz and 320 MHz.* <<more...>>
We all have 'em: tools that let us do things easier and faster. Some we buy, others we make. This is my first entry about one of my favorite tools: an Eagle ULP I wrote that lets me do cost estimates on boards I'm designing using real-time prices fetched from Digi-Key. <<more...>>
I'm writing a new book about doing FPGA design using Xilinx ISE WebPACK and the XuLA board. I've reproduced the preface for the book below. Here are the important points:
I recently received an email which contained the following question:
Well, despite the great choices you have made making the XuLA, I was wondering why you did not use a Cypress (e.g. cy7c67300) chipset (but instead you used a PIC) for the virtual JTAG over the USB. The Cypress would have given to the board the possibility of having a full fledged USB 2.0 comm. port after the FPGA is programmed, am I wrong? With the Cypress you could have used firmware available around the internet...
Also, if I do not mistake, instead of the PIC you could have used a FT2232D which next to the virtual JTAG it would have given a serial RS232, which is quite a good thing for FPGA. Did you consider this lack of serial comm.? <<more...>>
In my previous blog post, I showed a circuit I built to interface my XuLA FPGA board to a VGA monitor. What I didn't show was the code that lets the FPGA fetch an image from SDRAM and display it on a monitor. I'll try to remedy that in this post.
I'll start off with the basics of VGA video signals: signal levels and timing. Then I'll show you the block-level architecture of a module for generating VGA video and an application that uses the module to display an image stored in SDRAM. Finally, I'll post an archive of the Xilinx ISE 13 project files that compiles into a downloadable bitstream for the FPGA on the XuLA board. Hopefully you'll find enough comments in the VHDL code to understand how it all relates to what I'll describe below. (And for all who are about to ask: NO, I do not have a Verilog version of this.)
OK, here we go... <<more...>>