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Viewing posts from July, 2011

"Hard row to hoe. Came up with squat."

Posted by: Dave Vandenbout in Blog Post 5 years, 11 months ago

A few years ago, my sister and I decided to plant a stand of corn in addition to the regular garden on her farm. This entailed tilling a 50' x 15' area, hoeing the dirt up into about twenty mounds, shaping the mounds for holding water, punching four holes in each mound, and, finally, placing a few kernels in each hole. Then we planted beans among the mounds to try and crowd out the weeds. <<more...>>

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Amping the XuLA Clock Up To 300 MHz

Posted by: Dave Vandenbout in Blog Post 5 years, 11 months ago

Some people have commented that the 12 MHz clock on the XuLA FPGA board is too slow for practical use. What they've missed is the Spartan-3A FPGA has on-chip digital frequency synthesizers (DFS) that can multiply the clock to over 300 Mhz. To show how easy it is to do this, I've added another chapter on using the DFS to my new book about doing FPGA design using Xilinx ISE WebPACK and the XuLA board. It just takes a few lines of VHDL and you can have almost any clock frequency you want between 5 MHz and 320 MHz.* <<more...>>

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