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- XSA Board SDRAM Controller
- DESIGN FILES
- USING THE DESIGN EXAMPLE
- ENVIRONMENT
- SOURCE FILES
- AUTHOR
- COPYRIGHT AND LICENSE
- HISTORY
XSA Board SDRAM Controller
The XSA Board synchronous DRAM (SDRAM) controller core accepts simple read and write requests on the host-side and generates the timed waveforms required to perform these operations on the SDRAM. With pipelining enabled, read and write operations within a row of the SDRAM can be dispatched almost every clock cycle. The controller also manages the refresh operations needed to keep the SDRAM data valid, and will place the SDRAM in a self-refresh mode so data is retained even if the controller ceases operation.
A simple example that writes the SDRAM with random data and then verifies it is provided to show how the SDRAM controller is used.
DESIGN FILES
- common.vhd
This file contains some definitions and functions used in the rest of the VHDL code.
- memtest.vhd, randgen.vhd
These VHDL files describe a memory tester module that writes a stream of data from a random-number generator (RNG) to a storage
device and then reads the data back and compares it to the RNG output to verify it was stored correctly.
- sdramcntl.vhd
This VHDL file describes a controller that simplifies writing/reading data to/from an SDRAM.
You can read a more detailed explanation of the SDRAM controller at
http://www.xess.com/appnotes/an-071205-xsasdramcntl.pdf .
- xsasdramcntl.vhd
This VHDL file surrounds the generic SDRAM controller with a wrapper that customizes it for the XSA Boards.
- test_board_core.vhd
This file combines the generic memory tester and the SDRAM controller core to make the complete SDRAM tester.
- test_board.vhd
This file instantiates the test_board_core module to create an SDRAM tester for a particular model of XSA Board.
- test_board.ucf
This file contains the pin assignments for mapping the SDRAM tester to a particular board.
- test_board.npl
Open this project file with WebPACK if you need to recompile the design.
USING THE DESIGN EXAMPLE
- Step 1:
Attach a DC power supply to the XSA Board.
- Step 2:
Attach the downloading cable from the PC parallel port to the XSA Board.
- Step 3:
Set jumper J9 on the XSA Board to XS.
- Step 4:
Download the default parallel port interface into the XSA-3S1000 (\XSTOOLS\XSA\3S1000\dwnldpar.svf)
if it is not already present. (Running GXSTEST will do this automatically.)
- Step 5:
Download the test_board.bit file to the XSA Board.
- Step 6:
Once the test_board.bit file is downloaded into the XSA Board, the LED should display 2 => 3 => O
to indicate the SDRAM test completed successfully.
(An E will appear if an error occurred.)
ENVIRONMENT
This example design was developed using the following version of software:
Xilinx WebPACK : 6.3.03i
SOURCE FILES
You can download the source files for this example design from the XESS website at http://www.xess.com/projects/sdramtst-1_4.zip .
AUTHOR
Dave Vanden Bout, X Engineering Software Systems Corp.
Send bug reports to bugs@xess.com.
COPYRIGHT AND LICENSE
Copyright 2006 by X Engineering Software Systems Corporation.
This application can be freely distributed and modified as long as you do not remove the attributions to the author or his employer.
HISTORY
04/06/2006 - Initial release.